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[Internet-Network] mac_controller

Description: 用verilog编写实现的以太网控制器（MAC）源码，解压后用ISE打开工程即可。-Prepared using verilog implementation Ethernet Controller (MAC) source code, open the project after decompression can be used ISE.
Platform: | Size: 142336 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] ethernet_tri_mode.tar

Description: 基于verilog编写以太网激励程序源代码-Ethernet-based incentive program write verilog source code
Platform: | Size: 686080 | Author: 张鹏 | Hits:

[Program doc] FPGAEthernetVerilog

Description: 使用Verilog语言在FPGA平台上控制Ethernet上数据的发送与接收-FPGA realization using Verilog to control transmitting and receiving data over Ethernet
Platform: | Size: 6144 | Author: 白宇 | Hits:

[VHDL-FPGA-Verilog] ldpc_encoder_802_3an_latest.tar

Description: 适用于10GBase-T的以太网(802.3an协议)LDPC, VERILOG语言编写，可以应用在LATTICEXP2系列芯片上，基于Gallager算法。-LDPC encoder for 10GBase-T Ethernet (802.3an), based on Gallager s A algorithm
Platform: | Size: 620544 | Author: liang | Hits:

[VHDL-FPGA-Verilog] ethernet_controller_Verilog

Description: 以太网控制器源码，verilog语言,包含MAC、MII接口-Ethernet controller ,include MAC and MII interfaces ,by verilog
Platform: | Size: 71680 | Author: CL | Hits:

[VHDL-FPGA-Verilog] MACtop

Description: 基于FPGA的以太网控制器（MAC）源码，包括发送、接收、控制、CRC、寄存器、计数器等模块-Ethernet MAC sub-layer protocol
Platform: | Size: 128000 | Author: cmf | Hits:

[VHDL-FPGA-Verilog] ethernet10-100M-IP-core

Description: 以太网10-100M IP核Verilog源码，可综合-Ethernet 10-100M IP core Verilog source code can be integrated
Platform: | Size: 740352 | Author: owen | Hits:

[VHDL-FPGA-Verilog] ethmac

Description: 以太网的verilog代码，来自opencores网站。-Ethernet verilog code from opencores site.
Platform: | Size: 1805312 | Author: lvlv | Hits:

[VHDL-FPGA-Verilog] ethernet(MAC)verilog-langue

Description: 用veriolog编写以太网控制器（ＭＡＣ）-ｅｔｈｅｒｎｅｔ MAC of verilog
Platform: | Size: 138240 | Author: 刘大 | Hits:

[TCP/IP stack] MAC_verilog

Description: 以太网MAC网卡的Verilog源代码，可以节省TCP/IP协议的设计开发时间。-Verilog source code for Ethernet MAC network card, you can save the TCP/IP protocol design and development time.
Platform: | Size: 125952 | Author: lxk | Hits:

[Windows Develop] EEthhernet_vet

Description: Ethernet(以太网)verilog ip core用veriloggHDL语言写的以太网软核，对学习verilog语言与以太网有非常大帮助。 -Ethernet (Ethernet) Verilog the ip core with veriloggHDL language Ethernet soft-core, there is a very big help to learn verilog language and Ethernet.
Platform: | Size: 907264 | Author: 面积 | Hits:

[VHDL-FPGA-Verilog] MII

Description: 以太网MII芯片配置接口的VHDL设计，配置PHY芯片的模块设计-Ethernet MII chip configuration interface VHDL design, configuration PHY chip module design
Platform: | Size: 2048 | Author: 雷伟林 | Hits:

[VHDL-FPGA-Verilog] verilog-ip-core

Description: verilog ip核，源代码，ethernet， video_compression_systems-verilog ip core source code, ethernet, video_compression_systems
Platform: | Size: 3798016 | Author: 刘兵 | Hits:

[VHDL-FPGA-Verilog] EtherNet

Description: 以太网控制器的FPGA实现,用Verilog语言编写!-Ethernet controller FPGA, Verilog language!
Platform: | Size: 142336 | Author: Shawn | Hits:

[VHDL-FPGA-Verilog] 8b10b

Description: 8b10b编解码，用于光通信和千兆以太网，verilog编写，已验证-8b10b codec for optical communications and Gigabit Ethernet, verilog prepared Verified
Platform: | Size: 7168 | Author: 容易 | Hits:

[VHDL-FPGA-Verilog] ethernet.tar

Description: verilog写的以太网硬件模型，使用xilinx FPGA，ieee802.3ae-an ethernet model in Verilog，using a Xilinx FPGA，and the function：IEEE 802.3ae Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation
Platform: | Size: 788480 | Author: AricSnow | Hits:

[Other] MAC_verilog

Description: 以太网的verilog代码实现，希望提供有所帮助-Ethernet verilog code, I hope to provide helpful
Platform: | Size: 115712 | Author: 周思源 | Hits:

[VHDL-FPGA-Verilog] 10_100M-Ethernet-

Description: 10M 100M 以太网 Verilog 源代码-10M 100M Ethernet
Platform: | Size: 89088 | Author: horacedu | Hits:

[VC/MFC] Chapter10-Sample

Description: 以太网的verilog的应用软件开发程序，ise开发环境,对于相关设计人员有一定参考价值-Ethernet verilog application software development procedure, ise development environment, has certain reference value for related design personnel
Platform: | Size: 122880 | Author: lc | Hits:

[VHDL-FPGA-Verilog] ETH_SRC

Description: 网络接口源码实现，使用的是Verilog语言-ethernet Verilog
Platform: | Size: 1261568 | Author: 王长友 | Hits:
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